June 2026 Synopsys expanded its analog and mixed-signal IP portfolio with new 2nm process-ready interface and foundation IP optimized for AI, high-performance computing, and automotive semiconductor applications, enabling faster SoC development and improved power efficiency.
April 2026 Cadence Design Systems introduced an enhanced portfolio of analog and mixed-signal IP featuring advanced SerDes, PLL, and power management IP designed for next-generation automotive, data center, and edge AI chip designs.
January 2026 Alphawave Semi expanded its connectivity IP offerings with new high-speed mixed-signal PHY IP supporting advanced semiconductor process nodes, strengthening its portfolio for AI infrastructure and networking applications.